Dwarkesh walks through GPUs from NAND gates to systolic arrays
Two-hour blackboard session starts at logic gates and ends at why TPUs, FPGAs, and brains diverge in layout. You’ll get concrete intuition on data movement costs and pipeline registers that directly affects how you think about inference spend on Workers and Lambda.
https://x.com/dwarkesh_sp/status/2057857033659937220
New blackboard lecture w @reinerpope
How do chips actually work – starting with basic logic gates, and working up to why GPUs, TPUs, FPGAs, and the human brain each look the way they do.
0:00:00 – Building a multiply-accumulate from logic gates
0:16:20 – Muxes and the cost of data movement
0:25:59 – How systolic arrays work
0:39:00 – Clock cycles and pipeline registers
0:51:40 – FPGAs vs ASICs
1:03:14 – Cache vs scratchpad
1:07:16 – Why CPU cores are much bigger than GPU cores
1:11:49 – Brains vs chips
1:15:22 – A GPU is just a bunch of tiny TPUs
Look up Dwarkesh Podcast on YouTube/Spotify/etc to watch. Enjoy!May 22, 2026 View on X →
